processor performance

Experiments show that with less cost , split read and off-chip cache can bring a remarkable improvement to the processor performance .

测试结果表明，Split读和片外Cache能够以比较低的代价使处理器性能得到很大提高。

In audio applications , the single-instruction , multiple data ( SIMD ) mode effectively doubles the processor performance .

在音频应用中，单指令多数据（SIMD）模式实际上可使处理器性能提高一倍。

Fuzzy Comprehensive Assessment of Radar Signal Processor Performance

雷达信号处理机性能的模糊综合评判

Instruction supply can influence processor performance greatly .

取指令能力的高低对微处理器的性能有很大影响。

The Experimental Verification of the Digital Beamforming Processor Performance

雷达数字波束形成器性能的实验验证

In particular , as represented by floating point DSP processor performance considerably improved .

尤其是以DSP为代表的浮点处理器的性能有了相当的提升。

Split read and off-chip cache are used in this scheme to improve the processor performance .

该接口部件通过使用Split读和片外Cache来提高处理器的性能。

It is a library that helps you leverage multi-core processor performance without having to be a threading expert .

这种库可以帮助您充分利用多核处理器的性能，而无需掌握大量线程方面的专业知识。

The combination of DSP processors and reconfigurable computing technology has the promising potential to improve the single DSP processor performance to a higher level .

而可重构技术和DSP处理器的结合也使得单DSP处理器性能有望得到很大提升。

In recent years , Cloud computing has been widely adopted in massive data processing due to the higher processor performance , the higher reliability and scalability .

近年来，云计算因其高性能、高可靠、可扩展等特点在海量数据计算中得到了广泛应用。

With advancing in technology and processor performance increasing , neural networks , intelligent control and other advanced control algorithms will be widely applied to the APF .

随着科技技发展和处理器性能的提高，神经网络、知能控制等先进的控制算法将会广泛应用到APF中。

This translates to processor performance up to four times faster and graphics eight times as fast as last year 's model , according to Apple .

据苹果称，这使它与老款相比处理器性能快四倍，图形处理能力快八倍。

With the embedded processor performance increasing and the emergence of dedicated graphics acceleration chip , the embedded platform is possible for fast and high quality image processing .

随着嵌入式处理器性能的提升及专用图形加速芯片的出现，在嵌入式平台上实现快速且高质量的图像处理成为可能。

Due to the big gap between processor performance and memory performance , it results in the memory wall problem , namely , the memory system has become the bottleneck .

由于处理器性能和存储器性能的巨大差异，导致了存储墙问题的出现，使得存储系统成为系统的瓶颈。

To find the most appropriate cluster , processor performance and inter-processor communication performance both are measured for every cluster , and job runtimes are evaluated according to application performance model .

为找出最适合机群，对每个机群的处理机性能和处理机间通信性能进行测量，并根据应用性能模型预测作业运行时间。

The multicore architecture enhances the processor performance while there are many cores accessing the memory which need more memory bandwidth and deteriorate the ' memory wall ' problem .

采用多核体系结构能够提高处理器的性能，但多核处理器中有多个处理器核访问存储器，对存储系统带宽需求增加，存储墙问题表现更为突出，给存储系统设计带来了挑战。

Modern processor performance increases at a rat of 60 % per year , while the bandwidth of a DRAM chip increase by only 15 % - 20 % per year , with latency improved by only 7 % .

现代处理器性能以60%的年增长率飞速发展，相比之下，处于不同工艺下的DRAM的时滞和带宽的改进却分别只有7%和15～20%；

Simulation with its flexiblity and its accuracy on evaluation of the overall performance has been the primary tool for processor performance evaluation , but it is very time-consuming , and provides little insight into the various factors that determine the overall performance .

一直以来，模拟器以其灵活的方式和对处理器整体性能精确的评估，成为处理器性能评估的主要工具，但是用模拟的方式进行性能评估非常耗时，而且不能深刻洞察各种因素对处理器性能的影响。

Finally , MPEG decoding program is taken as an example to show the improvement of the processor performance by reducing the CPI value : 36 % compared to centralized method , and the hardware cost ( accounting for 3.7 % of the processor resources ) is small .

最后以MPEG解码程序为例，说明该策略以较小的硬件成本（占MD32资源的3.7%）有效地降低了CPI值，比集中式数据转发机制的处理性能提高了36%。

Signature instructions with weak position constraint are designed to offer the redundant control flow information , and these instructions can be executed in unoccupied instruction slots or in positions of NOP instructions to minimize the overhead on processor performance and program code size .

设计了弱位置约束的特征值指令，允许在一定范围内寻找空闲指令槽或NOP指令位置来执行特征值指令，由此减小了处理器的性能损失和代码长度开销。

The Application of Single Chip Processor to Performance Test for Motorized Vehicles

机动车辆性能测试中的单片机应用

High-Speed ADC of Signal Processor Dynamic Performance Testing

信号处理机的高速ADC模块动态性能在线测试

So , how to improve i-cache hit rate and enhance processor 's performance became a significant issue .

因此，如何提高指令Cache的性能，最大限度地发挥处理器性能成了人们所关心的一个焦点。

With the increasing requirement for the system resource , power consumption and processor 's performance in the design of the embedded products , it becomes more and more important for the code optimization .

随着嵌入式产品设计上对系统资源、功耗和处理器性能的要求越来越高，对嵌入式系统软件的优化显得愈发重要。

In this paper , arising from the use of multi-core processor hardware performance and object-oriented technology brought about by the development of more efficient parallel concurrent object-oriented technology with the integration , resulting in the object-oriented real-time three-dimensional parallel multi-threaded engine .

本文利用多核处理器所带来的硬件性能和面向对象技术所带来的开发效率的提升，将并行并发同面向对象技术融合，实现了面向对象的多线程并行实时三维引擎。

To realize the modern Radar signal processor with high performance provides guarantee .

为实现现代具有高性能的雷达信处机提供了保证。

It 's common to think that the processor frequency determines performance .

通常我们都认为是处理器的频率决定了性能的高低。

Besides the clock speed , the technology used in a processor can affect performance .

除时钟速度外，处理器使用的技术也会影响性能。

A Programmable Radar Signal Processor With Advanced Performance

一种高性能的可编程雷达信号处理机

It is essential not to confuse the frequency of a processor with its performance level .

重要的是不要混淆频率的处理器，其性能水平。